Normally, a metal oxide semiconductor (MOS) device is composed of a metal layer, a silicon oxide layer, and a substrate. Since the adhesion between the metal and the oxide is poor, a polysilicon material is often used to replace the metal so as to form the conductive layer of an MOS device. However, the disadvantage of the polysilicon material is that its resistance is higher than that of the metal. Although the resistance can be reduced by doping impurities, the generated conductivity is not high enough for a good conductive layer of an MOS device. A general solution is to add a metal silicide layer on the polysilicon layer, such as a tungsten silicide (WSi) layer, so as to improve the conductivity of the gate structure.
In prior art, a method of forming a contact structure comprises the following steps: forming a dielectric layer; forming a contact; and forming a metal layer. The general method for forming a metal contact between the metal layer and the substrate is the self-aligned contact etching method.
FIGS. 1A-1C represent a conventional method of forming a gate structure. The method is described as follows.
Referring to FIG. 1A, first, a substrate 2 is prepared. Next, a plurality of separated gate structures is formed on the substrate 2, wherein each gate structure comprises a first conductive layer 4, a second conductive layer 6, an insulating layer 8, and two sidewall spacers 10. A dielectric layer 12 is formed to cover the whole substrate after the gate structure is formed.
Referring to FIG. 1B, next a lithographic process and an etching process are performed to remove a selected portion of the dielectric layer 12 until the top surface of the substrate is exposed. The etching process also affects the insulating layer 8 and the sidewall spacer 10. Since the etching rate of the insulating layer 8 and the sidewall spacer 10 is lower than that of the dielectric layer 12, only portions of the insulating layer 8 and the sidewall spacer 10 are removed. As a result, a contact 20, which is formed between the gate structures, can be self-aligned to the substrate where a contact region is formed. As shown in the same figure, the contact region is formed on an exposed top surface of the substrate 2 with a width of X.
Referring now to FIG. 1C, a metal layer 14 is deposited to a specific thickness so as to cover the exposed surface of the substrate, the sidewall spacers 10 of the gate structures, and the substrate 2. In this way, a metal contact of the width of X is formed in the self-aligned contact 20 between the metal layer 14 and the substrate 2.
The contact resistance of the aforementioned self-aligned contact is proportional to the contact region (i.e., the region marked with the width X) between the metal layer 14 and the substrate 2. The contact region can be increased during the etching process by extending the etching time. However, if the etching time is not controlled properly, the method will overly etch the insulating layer 8 and the sidewall spacer 10 such that the second conductive layer 6 is exposed. The exposed part of the second conductive layer 6 will contact the metal layer 14 at point 16 and cause a short circuit.
In order to improve the above-mentioned conventional manufacturing process, U.S. Pat. No. 5,989,987 provides an improved method of forming a self-aligned contact structure, as shown FIGS. 2A-2D. The prior art method is described as follows.
Referring to FIG. 2A, first a substrate 2 is prepared. The substrate has a first conductive layer 4, a second conductive layer 6, and an insulating layer 8 formed in sequence from bottom to top. The first conductive layer 4 can be a polysilicon layer or an amorphous silicon layer. Next, a plurality of separated gate structures is formed by performing a dry etching step to the extent that the top surface of the substrate 2 is exposed.
Referring next to FIG. 2B, the second conductive layer 6 is etched with an etchant, which is a mixture of NH4OH, H2O2, and H2O. Although the purpose of the etchant is to etch the second conductive layer 6, the first conductive layer 4 is also etched at a slower etching rate. A sidewall spacer layer 10 is formed on each side of each gate structure after the etching step is finished.
Referring to FIG. 2C, a dielectric layer 12 is formed on the whole top surface of the substrate to cover all the gate structures and the exposed surface of the substrate. After that, selected portions of the dielectric layer 12 between the gate structures are removed until the top surface of the substrate 2 is exposed.
Referring then to FIG. 2D, a metal layer 14 of a specific thickness is deposited to cover the exposed surface of the dielectric layer 12, the sidewall spacers 10 of the gate structures, and the substrate 2. In this way, a metal contact is formed in a self-aligned contact 20 between the metal layer 14 and the substrate 2.
The advantage of the method of the aforementioned U.S. Pat. No. 5,989,987 resides in the extra etching step, which is performed on the second conductive layer 6. The width of the second conductive layer 6 is narrower than that of the above insulating layer 8 due to this extra etching process, so as to form a larger process window and to avoid a short circuit caused by the contact of the second conductive layer 6 and the metal layer 14 at point 16.
However, the method of forming a self-aligned contact structure provided by U.S. Pat. No. 5,989,987 has the following disadvantages:
(1) The etching step of the second conductive layer 6 is global. In other words, one side of the second conductive layer 6, which is not used to form bit-line contact, is also etched. Since the cross-section area of the second conductive layer 6 is reduced, the resistance of the gate conductor is increased accordingly.
(2) The etching step reduces the contact area between the second conductive layer 6 and the first conductive layer 4. The peeling phenomenon will be induced in subsequent manufacturing processes if too much contact area is reduced.